The present invention relates to a video RAM and more particularly to a method for arranging RAM column decoders and SAM column decoders within a video RAM.
Video RAMs have become an important and integral part of present computer systems, most notably laptop computers and notebook computers, and consumer electronics. A video RAM is a memory device providing two principal functions. The first function is that of a dynamic random-access-memory (RAM) device. The second function is that of a high speed serial-access-memory (SAM) device. Generally, the RAM and SAM functions can be asynchronously provided through dual access ports, a RAM port and a SAM port. The RAM port is typically connected to a CPU in the computer system. The SAM port is typically connected to the an external system such as a cathode-ray-tube (CRT) or video camera.
In order to provide the widest possible variety of operational capabilities and largest memory capacity, video RAMs have been integrated with increasing density. The two factors which must be addressed in realizing increased integration of video RAMs are data access speed and current consumption. Increased memory density necessarily increases the number of memory cells per unit area. Unavoidably, increased memory cells require an increased number of decoders. However, the increasing number of decoders adversely complicate the layout of the video RAM and impedes efforts to increase integration of the overall device. In particular, the RAM and SAM portions of the video RAM separately require, in their association with the unit memory cell array, independent column decoders. This arrangement will be further explained with reference to FIG. 1.
FIG. 1. illustrates an exemplary conventional arrangement of column decoders in a video RAM. The conventional layout is used, for example, in video RAM products KM424C257 and KM428C128 manufactured by Samsung Electronics Co., Ltd. Referring to FIG. 1, a column address signal derived from an external source is applied to column address input buffer 2. The output of column address input buffer 2, CAi, is applied to RAM column predecoder 4 and SAM counter 6. In turn, SAM counter 6 applies a SAM column address signal, SCAi to SAM column predecoder 8. Signal RDCAij is applied to a plurality of RAM column decoders 12 from RAM column predecoder 4. Similarly, another signal SDCAij is applied to a plurality of SAM column decoders 14 from SAM column predecoder 8. Each RAM column decoder 12 and each SAM column decoder 14 are arranged on either side of a corresponding memory subcell array 10. In the particular example shown in FIG. 1, there are four subcell arrays independently accessed by a corresponding RAM column decoder 12 and a SAM column decoder 14.
In the foregoing arrangement, SAM column predecoder 8 is remotely located from SAM column decoder 14. This arrangement uses chip space inefficiently and impedes efforts to further integrate the video RAM. Additionally, the excessively long signal line(s) between SAM column predecoder 8 and SAM column decoder 14 develop a loading capacitance which adversely affects current drain.
FIG. 2 illustrates in greater detail the layout of, and respective relationships between RAM column decoder 12, SAM column decoder 14, and subcell array 10 of FIG. 1. RAM column decoder 12 and SAM column decoder 14 respectively comprise column decoder portions #0, #1, . . . #i. Each column decoder portion is typically responsive to a portion of the respective predecoder address signals RDCAij and SDCAij. For example, RAM column decoder portion #0 generates a first RAM column select line signal, RCSL0, in response to RDCAij or a portion thereof. RCSL0 switches transistors 22 and 24 according to its binary logic level (high=1, or low=0). RAM input/output lines (RIO and RIO) are respectively connected to the channel paths of transistors 22 and 24. A similar exemplary relationship exists between SAM column decoder portion #0, first SAM column select line signal, SCSL0, transistors 26 and 28, and SIO and SIO.
Subcell array 10 comprises RAM cell array 10A connected to RAM column decoder 12, and SAM cell array 10B connected to SAM column decoder 14. Data is read from, or written to RAM cell array 10A through RIO and RIO. Data is read from, or written to SAM cell array 10B through SIO and SIO. Since RAM column decoder 12 and SAM column decoder 14 are arranged on opposite sides of subcell array 10, separate power supply lines must be provided to each decoder. This requirement creates an inefficient layout, and causes increased power line noise within the video RAM.